1. Field of the Invention
The present invention relates to charge pumps, and methods and apparatus for reducing power supply current surges in a charge pump.
2. Description of Related Art
U.S. Pat. No. 5,629,890 to Engh relates to an integrated circuit system for analog signal storage which incorporates a read-while-write programming method. In the read-while-write programming method of the '890 patent, a high voltage ramp is applied to a memory cell to program the memory cell to a target voltage. FIG. 1 illustrates the charge pump circuit 100 that provides the high output voltage during writing/programming of a memory cell. As shown in FIG. 1, the charge pump circuit 100 includes two charge pump lines, each charge pump line having a plurality of charge pump stages 110A.sub.1 -110A.sub.n and 110B.sub.1 -110B.sub.n, respectively. Each of the charge pump stages 110A.sub.1 -110A.sub.n and 110B.sub.1 -110B.sub.n includes a respective capacitor CA.sub.1 -CA.sub.n and CB.sub.1 -CB.sub.n, and a respective N-channel device MA.sub.1 -MA.sub.n and MB.sub.1 -MB.sub.n, each connected as a diode. A plurality of clock sources CLK1, CLK1B, CLK2, and CLK2B are provided, with alternate stages of each charge pump being connected to a common clock signal.
FIG. 2A illustrates a timing diagram of the prior art charge pump clock signals. As can be seen from the Figure, clock signals CLK1 and CLK1B, as well as clock signals CLK2 and CLK2B, are non-overlapping. Thus, clock signals CLK1 and CLK1B are never both high at the same time, and clock signals CLK2 and CLK2B are never both high at the same time. The operation of the circuit of FIG. 1 may be described as follows. (In this description, it will be assumed that the diode voltage drop of all of the diode-connected transistors in FIG. 1 is equal to V.sub.d and that the clock signals swing between zero or ground and V.sub.dd.) When clock signal CLK1 is low, capacitor CA1 will charge to a voltage V.sub.dd -V.sub.d, where V.sub.d is the diode voltage drop of diode-connected transistor MA.sub.0. When clock signal CLK1 goes high, the voltage at node A.sub.0 will rise toward 2 V.sub.dd -V.sub.d. If the voltage at node A1 is presently less than 2 V.sub.dd -2 V.sub.d (clock signal CLK1B being low), diode-connected transistor MA.sub.1 will become forward biased, dumping some of the charge from capacitor CA.sub.1 to capacitor CA.sub.2.
On the other hand, if the voltage at node A.sub.1 is just equal to 2 V.sub.dd -2 V.sub.d, diode-connected transistor MA.sub.2 will be just on the threshold of conducting, though no substantial charge will be transferred from capacitor CA.sub.1 to capacitor CA.sub.2. When the clock signal CLK1 goes low again, diode-connected transistor MA.sub.1 will be reverse biased. When clock signal CLK1B goes high, the voltage on node A.sub.1 will increase from 2 V.sub.dd -2 V.sub.d toward 3 V.sub.dd -2 V.sub.d. If at this time the voltage on node A.sub.2 is less than 3 V.sub.dd -3 V.sub.d, part of the charge from capacitor CA.sub.2 will be dumped into capacitor CA.sub.3. If, on the other hand, the voltage on node A.sub.2 is just equal to 3 V.sub.dd -3 V.sub.d, diode-connected transistor MA.sub.2 will be just on the threshold of conducting, though again no substantial charge will be transferred from capacitor CA.sub.2 to capacitor CA.sub.3. Thus, carrying out this analysis to the limit, it may be seen that for n charge pump stages, the charge pump voltage limit for an unloaded (open circuit) charge pump output will be equal to N(V.sub.dd -V.sub.d).
For any real load on the charge pump, output capacitor CA.sub.n and CB.sub.n will discharge somewhat between pumping cycles to provide the output current into the load, in which case each stage of the two charge pump lines will pump charge toward the output at a rate dependent upon the charge pump output current. Accordingly, the charge pump circuit will appear as a voltage source with a source impedance inversely proportional to the size of the capacitors times the frequency of the clock signals.
In the read-while-write programming method, a read operation is simultaneously performed while the memory cell is being programmed to determine when to terminate the application of the high voltage (i.e., when the target voltage is reached). Since the reading occurs during the writing operation, the charge pump circuit 100 of FIG. 1 is active when the voltage stored on the cell is being read back. Depending on the number of charge pump stages, the loading on each of the clock drivers of the prior art is relatively large, being proportional to (n*C)/2, where n is the number of charge pump stages and C is the value of each capacitor. Driving a large load requires a large clock driver, which in turn increases the demand on the power supply. Large demands on the power supply cause current surges which cause undesirable disturbances in the system. FIG. 2B schematically illustrates the current surges on the power supply with reference to clocks CLK1, CLK1B, CLK2, and CLK2B.
The large current surges can result in inaccurate reading of the memory cell in the read-while-write programming method. As a result, the memory cell may be underprogrammed or overprogrammed. Also with the prior art charge pump, additional circuitry is needed to ensure that clocks CLK1 and CLK1B are non-overlapping and clocks CLK2 and CLK2B are non-overlapping. Further, as the demand continues for smaller die sizes, new design techniques and system implementations are needed to reduce the die area for any intended function.
Accordingly, there is a need in the art for an apparatus and method of providing a high voltage charge pump that outputs a high voltage while reducing instantaneous power supply current surges and reducing the overall size of the circuit.